Shift Registers

A shift register is a special type of register that will shift data with each clock cycle.  This type of setup is useful if data is being sent across or received from a single data line.  It's also useful for some mathematical operations such as division.  Shift registers can be loaded either in series or in parallel (or both) depending on what it's being used for.  Data can also be accessed in series or in parallel (or both) depending on what the shift register is being used for.  Serial loading/accessing means that the bits are loaded or accessed in order one at a time.  Parallel loading/accessing means that the bits are loaded or accessed at once.

The following is an example of a shift register with only serial loading available.  The register's individual parts are represented in block diagram in order keep the size of the image down.  This particular register is labeled so that the highest-value bit is loaded first and the lowest-value bit is loaded last, but you can load the bits in the opposite order if you want to (or need).  The important thing is that you are consistent with the order in which data is loaded into and accessed from the register.  The write enable input in this example is active low.

Some shift registers have the ability to load data in parallel.  The following is an example of such a register which also has the ability to shift data in from another register.  This feature is useful for expanding the size of a register as much as you need.  The shift register shown below has two inputs for loading and shifting data.  If the shift input is 1, then data will be shifted towards Q3.  The shift input overrides the load input.  If shift is 0 and load is 1, then all of the D input bits will be loaded into the shift register at once.  If both the load and shift inputs are 0, then then the shift register will hold its value.  Both the shift and load inputs in the example below are active high.

In the example above, there is only one Q output at the most significant bit.  Some registers have both parallel load and parallel read while others have one or the other.