- Published: Tuesday, 27 February 2018 12:39
- Written by Timothy Chapman
The D flip-flop, and other flip-flops derived from it, can have asynchronous set and reset inputs that will force the flip-flop to hold a specific value regardless of the other inputs.
Because you can build an edge-triggered flip-flop out of NAND or NOR gates, the method for asynchronously setting a 1 or 0 into the flip-flop will vary slightly. The gate of the latch is made of two latches wired to each other, which results in the gate itself storing the value of D on the clock trigger. To make it easier to demonstrate what's going on, the logic gates in the latch's gate will be numbered 1-4 from top to bottom. For the set or reset inputs, one input will go to gates 1, 3 and Q, while the other will go to gates 2, 4 and not Q. Here's an illustration with a positive-edge-triggered D flip-flop (left) and negative-edge-triggered D flip-flop (right).
In the image above, there is no priority given to S or R. As a result, if they are both active at the same time, then the latch will go to an invalid state. Once that happens, the input to go inactive will lose control of the flip-flop to the input that is still active. If both S and R go inactive at the exact same time (which is unlikely), then the latch may oscillate until the random variations in gate delays causes the latch to settle on a random value. Digital logic simulators tend to not like this.
Asynchronous set and reset for a D flip-flop made of NAND gates will be active low. The set input will go to 1, 3 and Q while the reset input will go to 2, 4 and not Q. When R goes low, the flip-flop is forced to store 0 even if both Clk and D are high. The flip-flop will then stay at zero when R goes high until the next clock trigger. S will force the flip-flop to store 1. The reason that S and R are active low is to save on transistors. Adding a NOT gate to the inputs would make them active high.
If your D flip-flop is made of NOR latches, then S and R will be active high by default. The S and R inputs will also be in the opposite locations from that of the positive-edge-triggered D flip-flop. So S goes to gates 2, 4 and not Q while R goes to gates 1, 3 and Q. Just like with the NAND latch, once S or R are toggled, the latch will store 1 or 0 respectively until the next clock trigger.